A level shifting circuit, also known as a voltage translator circuit, is used to shift the voltage levels of logic signals to higher voltages. For example, in a circuit where the logic levels are 0 volts for a “low” logic level and +1.2 volts for a “high” logic level, a level shifting circuit can be used so that those logic levels are 0 volts for the “low” logic level and +3.3 volts for the “high” logic level, in one example.
In one application, a translator circuit may be used to translate CMOS signal levels on a low power supply (i.e., internal levels from the core of a semiconductor device) to a higher power supply (i.e., I/O levels).
FIG. 1 illustrates an example of a level shifting circuit 10 which shifts the voltage levels of a logic signal 12 to a higher voltage level at output 14. In this example, a pair of p-channel transistors Q1, Q2 are employed with their sources connected to a high voltage supply 16 and their gates/drains cross coupled in a positive feedback configuration. Cross-coupled nodes 18, 20 are also connected to a pair of n-channel pull down transistors Q3, Q4. The pull down transistors Q3, Q4 will force one side or the other side of Q1/Q2 low while the cross coupling will force the opposite side of Q1/Q2 high, such as writing a soft latch. The signal levels at the gates of Q3 and Q4 are low voltage. The signal level at the cross-coupled nodes 18, 20 are high voltage thus accomplishing the translation or level shifting function.
In FIG. 1, the output stage includes an n-channel pull-down transistor Q8 driven by a low voltage signal 22 and a p-channel pull-up transistor Q7 driven by a high voltage signal 24. This stage is used to increase drive strength and to help balance rise and fall delays.
As recognized by the present inventor, the circuit 10 of FIG. 1 may be characterized by slow response times. Further, the transistors may need to be sized such that the n-channel transistors are relatively large so they can force the circuit to the opposite state over process, temperature, voltage variations/corners. The much weaker p-channel transistors may present relatively slow rise times, may create large propagation delay and duty cycle distortion, and may skew the output signal 14.
As recognized by the present inventor, what is needed is a circuit for shifting the voltage levels of an input signal to higher voltage levels, while reducing the rise time and delay associated with the level shifting circuit.
It is against this background that various embodiments of the present invention were developed.